Deep submicron microprocessor design issues

0272-1732/99/$10.00  1999 IEEE Deep-submicron technology allows billions of transistors on a single die, potentially running at gigahertz frequencies. According to Semiconductor Industry Association (SIA) projections, the number of transistors per chip and the local clock frequencies for high-performance microprocessors will continue to grow exponentially in the near future, as Figure 1 (on the next page) illustrates. This ensures that future microprocessors will become ever more complex. However, physical and program behavioral constraints will limit the usefulness of this complexity. Physical constraints include interconnect and device limits, as well as practical limits on power and cost. Program behavioral constraints result from program control and data dependencies, and from unpredictable events during execution. Other challenges include the need for advanced CAD tools to combat the negative effect of greater complexity on design time. Designers will also have to make improvements to preserve computational integrity, reliability, and diagnostic features. Successful implementations will depend on the processor architect’s ability to foresee technology trends and understand the changing design trade-offs for specific applications, beginning with the differing requirements for client versus server processors. This article discusses these trade-offs in light of industry projections and the many considerations affecting deepsubmicron technology.